A Level Computer Science 9618: RISC vs CISC, Pipelining and Interrupts

A hardware company is designing two new processors.

Processor X has a small, fixed set of simple instructions, almost all of which complete in exactly one clock cycle. It relies on a large bank of general-purpose registers, and it only accesses main memory using dedicated load and store instructions.

Processor Y has a much larger and more varied set of instructions. Some of these instructions operate directly on data held in main memory (not just in registers), and completing them can take several clock cycles rather than one.

(a) State, giving a reason for each, which processor is RISC and which is CISC. [3]

(b) Processor X uses a three-stage pipeline (Fetch, Decode, Execute) to overlap the execution of successive instructions. The table below shows which pipeline stage three instructions, I1, I2 and I3, occupy in each clock cycle, assuming no stalls occur.

Cycle	1	2	3	4	5
I1	F	D	E
I2		F	D	E
I3			?	?	?

(i) Complete the table to show which stage I3 occupies in cycles 3, 4 and 5. [1]

(ii) State the total number of clock cycles taken to complete all three instructions using this pipeline, and the total number of clock cycles that would instead be needed if the three instructions were executed one at a time with no overlap at all. [1]

(c) Explain why the maximum time between an interrupt occurring and Processor X (RISC) beginning to service it is more predictable than the equivalent maximum time for Processor Y (CISC). [2]

Part (a): Identifying RISC and CISC

RISC (Reduced Instruction Set Computer) processors use a small, simple instruction set, where almost every instruction completes in a single clock cycle. Because the instruction set is kept simple, RISC processors rely on having many general-purpose registers, so that data can be kept in registers rather than repeatedly accessed from memory; memory is only accessed deliberately, through dedicated load and store instructions.

CISC (Complex Instruction Set Computer) processors use a larger, more varied instruction set. Individual CISC instructions can do more work, including operating directly on data held in memory rather than only in registers, but as a result some instructions take several clock cycles to complete rather than one.

Matching this to the scenario:

Processor X is RISC: it has a small, fixed set of simple, almost-always single-cycle instructions, a large register bank, and it only touches memory through dedicated load/store instructions, exactly the RISC pattern. [1 mark for identifying X as RISC, with reason]
Processor Y is CISC: it has a larger, more varied instruction set, some instructions take several clock cycles, and some instructions operate directly on memory rather than only on registers, exactly the CISC pattern. [1 mark for identifying Y as CISC, with reason]
[1 further mark] for correctly linking the register bank / single-cycle timing to RISC and the direct-memory-access / variable-cycle timing to CISC, rather than the two being reversed.

Part (b): Pipelining

(i) Completing the pipeline table

Once the pipeline is running smoothly, each instruction enters the Fetch stage exactly one cycle after the previous instruction did, then moves one stage further per cycle. I3 therefore follows the same one-cycle-later pattern as I2 followed I1:

Cycle	1	2	3	4	5
I1	F	D	E
I2		F	D	E
I3			F	D	E

So I3 occupies F in cycle 3, D in cycle 4, and E in cycle 5. [1 mark]

(ii) Total clock cycles, pipelined vs non-pipelined

With the pipeline, the last instruction (I3) finishes at the end of cycle 5, so all three instructions complete in 5 clock cycles in total. In general, for a k-stage pipeline running n instructions with no stalls, the total time is k + (n - 1) cycles: here 3 + (3 - 1) = 5, which matches the table.

Without any overlap at all, each instruction would have to completely finish its three stages (Fetch, Decode, Execute. 3 cycles) before the next instruction could even begin. For three instructions, that is 3 x 3 = 9 clock cycles in total.

So pipelining reduces the time for these three instructions from 9 cycles down to 5 cycles. [1 mark for both totals correct]

Part (c): Interrupt response predictability

Processor X’s (RISC) instructions are simple and uniform, and almost all of them complete in exactly one, fixed-length clock cycle. This means that no matter which instruction happens to be executing at the moment an interrupt occurs, the processor only ever has to wait a short, fixed, predictable amount of time (at most one clock cycle) for that instruction to finish before it can respond to the interrupt.

Processor Y’s (CISC) instructions vary enormously in how long they take: some finish in one cycle, but others, especially those that operate directly on memory, can take many clock cycles to complete. If an interrupt occurs just as one of these long, multi-cycle instructions has begun, the processor may have to wait considerably longer, and by an amount that is much harder to predict in advance, before that instruction finishes and the interrupt can be serviced.

So RISC’s uniform, short instruction timing gives a predictable, bounded worst-case delay before an interrupt is serviced, whereas CISC’s widely varying instruction timing means the worst-case delay is both longer and less predictable. [2 marks: 1 for RISC’s uniform single-cycle timing giving a bounded wait, 1 for CISC’s variable, sometimes multi-cycle timing giving a longer, less predictable wait]

Final answers

(a) Processor X is RISC (simple, single-cycle instructions; large register bank; memory only via load/store). Processor Y is CISC (larger, variable-length instruction set; some multi-cycle instructions; direct memory operands).
(b)(i) I3: F (cycle 3), D (cycle 4), E (cycle 5)
(b)(ii) Pipelined: 5 cycles in total. Non-pipelined: 9 cycles in total.
(c) RISC’s uniform, single-cycle instructions give a short, predictable maximum wait before an interrupt is serviced; CISC’s variable, sometimes multi-cycle instructions give a longer, less predictable maximum wait.