Processor Architectures and Boolean Algebra: Question 7

Worked solution

Part (a): Instruction count. RISC vs CISC

RISC processors provide only a small set of simple instructions: arithmetic and logical operations work on registers, and memory is accessed only through dedicated load and store instructions. To add a value from one memory location to a value in another and store the result back, a RISC routine must therefore:

1. LOAD the first value from memory into a register,
2. LOAD the second value from memory into another register,
3. ADD the two register values together,
4. STORE the result from a register back into memory.

That is at least four separate instructions. A CISC processor, in contrast, can provide a single, more powerful instruction capable of operating directly on memory operands. For example, one instruction that reads both memory values, adds them, and writes the result back to memory, all as one complex instruction (or at least in fewer instructions than RISC needs).

So the RISC version is likely to contain more individual instructions, because each RISC instruction does less work, so more of them are needed to achieve the same task. [2 marks: 1 for correctly identifying RISC as having more instructions, 1 for the correct reason. RISC’s simple instructions require separate load/store steps that a single CISC instruction can combine]

Part (b): Compiler complexity

Because the RISC routine from part (a) needs more, simpler instructions to do the same job, the RISC compiler has more work to do to produce efficient code: it must decide how to schedule a larger number of instructions, and it must allocate values to RISC’s large bank of general-purpose registers effectively, to avoid wasting clock cycles. The CISC compiler can rely more directly on the processor’s complex instructions. Much of the work of combining several low-level operations is handled by the hardware itself, so the compiler does not need to perform as much scheduling and register-allocation optimisation to get reasonably efficient code.

So the RISC processor’s compiler needs to carry out more work, because simple instructions shift the burden of producing efficient code from the hardware onto the compiler. [2 marks: 1 for correctly identifying the RISC compiler as needing to do more work, 1 for the correct reason. More numerous simple instructions requiring more scheduling and register-allocation effort]

Part (c): Pipelining, throughput and single-instruction latency

A 4-stage pipeline means every instruction passes through the stages Fetch, Decode, Execute and Write-back, one after another. Considered entirely on its own, a single instruction still has to go through all four stages in sequence, so it still takes four clock cycles from start to finish. Pipelining does not remove any of these stages or make any one of them faster, so the time to complete one instruction in isolation is unchanged.

What pipelining changes is how many instructions can be in progress at once. Once the pipeline is full, a new instruction can begin the Fetch stage on every clock cycle, while earlier instructions are simultaneously in their own Decode, Execute or Write-back stages. This means that, after the pipeline first fills, one instruction reaches Write-back (i.e. completes) on every clock cycle, instead of the processor having to wait four full cycles between completed instructions as it would with no overlap at all.

So pipelining increases throughput. The rate at which instructions are completed over many instructions. Without reducing the latency of any single instruction, which still takes four cycles to pass through the pipeline. [2 marks: 1 for correctly explaining that a single instruction still takes the full four cycles/stages, 1 for correctly explaining that overlapping different instructions in different stages increases the rate of completion (throughput) once the pipeline is full]

Final answers

• (a) The RISC version has more instructions, since RISC’s simple load/store/arithmetic instructions must be used separately, whereas CISC can combine the load, add and store into fewer, more powerful instructions.
• (b) The RISC compiler needs to do more work, scheduling more instructions and allocating registers efficiently, since RISC’s simplicity shifts this burden from hardware to the compiler.
• (c) Pipelining does not shorten a single instruction’s four-cycle journey through the pipeline, but it increases throughput because a new instruction can complete on every clock cycle once the pipeline is full.