Studyledge

Processor Fundamentals and Assembly Language: Question 2

Syllabus 4.1

Structured AS 8 marks

A computer follows the Von Neumann model of computer architecture: a single main memory stores both program instructions and data, and each instruction is fetched into the CPU one at a time using the fetch-execute cycle. The CPU is connected to main memory by three buses: the address bus, the data bus and the control bus.

(a) State the purpose of each of these four special-purpose registers during the fetch part of the fetch-execute cycle: the Program Counter (PC), the Memory Address Register (MAR), the Memory Data Register (MDR) and the Current Instruction Register (CIR). [4]

(b) Using register transfer notation, write the two steps of the fetch stage that copy the address held in the PC into the MAR, and then update the PC so it is ready for the next fetch. [2]

(c) State the effect on a computer system of (i) increasing the width of the address bus, and (ii) increasing the width of the data bus. [2]

Show worked solution Hide worked solution

Worked solution

Part (a): Purpose of PC, MAR, MDR and CIR

  • PC (Program Counter): holds the address of the next instruction to be fetched from main memory.
  • MAR (Memory Address Register): holds the address of the memory location that is currently being accessed (this address is copied from the PC at the start of the fetch stage).
  • MDR (Memory Data Register): holds the data or instruction that has just been read from (or is about to be written to) the memory location addressed by the MAR.
  • CIR (Current Instruction Register): holds the instruction that has just been fetched, copied from the MDR, ready to be decoded and executed.

[4 marks]: 1 mark for each register’s purpose correctly stated.

Part (b): Register transfer notation for the fetch stage

MAR ← [PC]
PC ← [PC] + 1

The first line copies the address currently held in the PC into the MAR, so that this address can be used to access memory. The second line then increments the PC by 1, so that it is ready to point to the address of the following instruction for the next fetch-execute cycle.

[2 marks]: 1 for MAR ← [PC], 1 for PC ← [PC] + 1.

Part (c): Effect of bus width

(i) Increasing the width of the address bus increases the number of separate memory locations the CPU can directly address (an n-bit address bus can address 2^n locations), so a wider address bus allows a larger maximum size of main memory to be used.

(ii) Increasing the width of the data bus increases the number of bits that can be transferred between the CPU and main memory in a single bus cycle, so more data (or a longer instruction) can move per cycle, which can improve the processor’s overall processing speed.

[2 marks]: 1 for (i), 1 for (ii).

Final answers

  • (a) PC = address of next instruction; MAR = address currently being accessed; MDR = data/instruction just read (or to be written); CIR = the fetched instruction, ready for decoding.
  • (b) MAR ← [PC] then PC ← [PC] + 1
  • (c) (i) more memory locations can be directly addressed; (ii) more bits can be transferred per bus cycle.