Processor Fundamentals and Assembly Language: Computer Science 9618 (Cambridge International AS & A Level)

A student lists several features of a computer system and wants to identify which one is a genuine factor affecting the performance of the CPU itself, rather than a feature of a different component.

Which of these is a factor that directly affects the performance of a CPU?

A computer follows the Von Neumann model of computer architecture: a single main memory stores both program instructions and data, and each instruction is fetched into the CPU one at a time using the fetch-execute cycle. The CPU is connected to main memory by three buses: the address bus, the data bus and the control bus.

(a) State the purpose of each of these four special-purpose registers during the fetch part of the fetch-execute cycle: the Program Counter (PC), the Memory Address Register (MAR), the Memory Data Register (MDR) and the Current Instruction Register (CIR). [4]

(b) Using register transfer notation, write the two steps of the fetch stage that copy the address held in the PC into the MAR, and then update the PC so it is ready for the next fetch. [2]

(c) State the effect on a computer system of (i) increasing the width of the address bus, and (ii) increasing the width of the data bus. [2]

A washing machine's embedded computer runs a wash-cycle-timing program in a continuous fetch-execute cycle. A "door open" sensor can generate a hardware interrupt at any moment while this program is running, and the processor must respond to it correctly without permanently losing its place in the wash-cycle program.

(a) State when, in relation to the fetch-execute cycle, the CPU checks whether an interrupt is pending. [1]

(b) Describe the sequence of actions the CPU carries out immediately after it detects the pending interrupt, up to the point where the interrupt service routine (ISR) begins to execute. [3]

(c) Explain what must happen once the ISR has finished executing, so that the wash-cycle-timing program resumes correctly. [2]

A processor has two registers available for general use: the Accumulator (ACC) and the Index Register (IX). It also has a Status Register (SR), which stores flags set by instructions such as CMP.

The table below shows the meaning of each opcode used in the program in this question.

The contents of main memory before the program runs are:

Address 63 will be used to store a running total. Addresses 60 and 61 hold two data values to be added together; address 62 holds a sentinel value of 0, marking the end of the list of values to be summed.

The program stored in memory is:

40  LDM #0
41  STO 63
42  LDR #0
43  LDX 60
44  CMP #0
45  JPE 50
46  ADD 63
47  STO 63
48  INC IX
49  JMP 43
50  LDD 63
51  END

(a) Identify the addressing mode used by each of these instructions from the program: LDM #0, STO 63, LDX 60. [3]

(b) State the purpose of the value 0 stored at address 62 in this program. [1]

(c) State the name of the register whose flags are updated when the instruction CMP #0 executes, and state one type of event, other than a compare instruction, that can set flags in this register. [2]

(d) Complete a trace table for this program, showing the value of ACC, IX and the contents of address 63 after each instruction executes, and state the final value that is left in ACC when the program ends. [5]

A processor's instruction set includes the indirect-addressing instruction LDI <address>, which loads into ACC the contents of the address that is itself stored at <address> (rather than the contents of <address> directly, as LDD <address> would). It also includes OUT, which sends the character whose ASCII value is currently held in ACC to the screen.

Some ASCII character codes: 65 represents the character 'A'.

The contents of main memory before the program runs are:

The program stored in memory is:

30  LDI 70
31  OUT
32  END

(a) Explain how the indirect addressing used by LDI 70 finds the value that is loaded into ACC, referring to address 70 and address 80 in this scenario. [2]

(b) Trace the execution of this program, stating the value held in ACC after each instruction executes. [2]

(c) State the character that is output when this program runs, and identify which instruction is responsible for producing this output. [2]

An embedded control register stores eight status flags, one per bit, numbered bit 0 (least significant) to bit 7 (most significant). A programmer wants to test whether bit 4 of this register is set to 1, without changing the contents of the register itself.

Which mask and operation correctly tests whether bit 4 is set to 1?

A processor register holds the 8-bit two's complement value 11101000. Three kinds of shift are available:

• a logical shift moves every bit left or right by a stated number of places, filling any vacated bit positions with 0.
• an arithmetic shift moves every bit left or right by a stated number of places, but on a right shift the sign bit (the most significant bit) is preserved, and vacated positions are filled with copies of the original sign bit, so the value is treated as a signed two's complement number.
• a cyclic shift moves every bit left or right by a stated number of places, but any bit shifted out of one end of the register re-enters at the opposite end, so no bits are lost.

Each part below applies a shift to the original, unchanged value 11101000.

(a) State the result, in binary, of applying a logical shift left by 1 place to 11101000, and state the denary value of this result if it is interpreted as an unsigned 8-bit binary integer. [2]

(b) State the result, in binary, of applying an arithmetic shift right by 1 place to 11101000, and state the denary value of this result if it is interpreted as a signed two's complement integer. [2]

(c) State the result, in binary, of applying a cyclic shift left by 3 places to 11101000. [2]

A register named REG in a data-logging device starts with the 8-bit value 10110010, where each bit records the on/off state of a separate sensor. Each part below uses a different bitwise mask on the original, unchanged value of REG (10110010) to carry out a different task.

(a) REG is ANDed with the mask 00100000. State the 8-bit binary result, and use it to state whether bit 5 of REG is set to 1 or set to 0. [2]

(b) REG is ORed with the mask 00000100, so that bit 2 is forced to 1 without disturbing any other bit. State the 8-bit binary result, and explain why every bit of REG other than bit 2 is guaranteed to be unchanged by this operation. [2]

(c) REG is XORed with the mask 00000001. State the 8-bit binary result, and state the general effect that XORing any single bit with a mask bit of 1 has on that bit. [2]

A processor has an Accumulator (ACC). The table below shows the meaning of each opcode used in the program in this question.

The program stored in memory is:

20  LDM #3
21  DEC ACC
22  CMP #0
23  JPN -2
24  END

(a) Identify the addressing mode used by LDM #3, and identify the addressing mode used by JPN -2. [2]

(b) The instruction JPN -2 at address 23 is executed for the first time. State the address that execution jumps to, showing how this address is calculated from the operand -2. [2]

(c) Complete a trace of this program, stating the value of ACC after each instruction executes, and state how many times in total the instruction DEC ACC executes before the program ends. [4]

A student writes four statements about the Von Neumann architecture used in most general-purpose computers, and wants to identify which one is genuinely correct.

Which of these statements correctly describes a feature of the Von Neumann architecture?