Processor Fundamentals and Assembly Language: Question 4

Syllabus 4.2

Structured AS 11 marks

A processor has two registers available for general use: the Accumulator (ACC) and the Index Register (IX). It also has a Status Register (SR), which stores flags set by instructions such as CMP.

The table below shows the meaning of each opcode used in the program in this question.

Opcode	Operand	Meaning
`LDM`	`#n`	Immediate addressing. Load the number n to ACC.
`LDR`	`#n`	Immediate addressing. Load the number n to IX.
`LDX`	`<address>`	Indexed addressing. Load the contents of (`<address>` + IX) to ACC.
`STO`	`<address>`	Direct addressing. Store the contents of ACC at `<address>`.
`ADD`	`<address>`	Direct addressing. Add the contents of `<address>` to ACC.
`CMP`	`#n`	Compare the contents of ACC with the number n.
`JPE`	`<address>`	Following a compare instruction, jump to `<address>` if the compare was True.
`INC`	`<register>`	Add 1 to the contents of the register (ACC or IX).
`JMP`	`<address>`	Jump to `<address>`.
`LDD`	`<address>`	Direct addressing. Load the contents of `<address>` to ACC.
`END`		Return control to the operating system.

The contents of main memory before the program runs are:

Address	60	61	62	63
Data	4	6	0	0

Address 63 will be used to store a running total. Addresses 60 and 61 hold two data values to be added together; address 62 holds a sentinel value of 0, marking the end of the list of values to be summed.

The program stored in memory is:

40  LDM #0
41  STO 63
42  LDR #0
43  LDX 60
44  CMP #0
45  JPE 50
46  ADD 63
47  STO 63
48  INC IX
49  JMP 43
50  LDD 63
51  END

(a) Identify the addressing mode used by each of these instructions from the program: LDM #0, STO 63, LDX 60. [3]

(b) State the purpose of the value 0 stored at address 62 in this program. [1]

(c) State the name of the register whose flags are updated when the instruction CMP #0 executes, and state one type of event, other than a compare instruction, that can set flags in this register. [2]

(d) Complete a trace table for this program, showing the value of ACC, IX and the contents of address 63 after each instruction executes, and state the final value that is left in ACC when the program ends. [5]

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Part (a): Addressing modes

LDM #0 uses immediate addressing. The value 0 is given directly in the instruction (shown by the #), and is loaded straight into ACC.
STO 63 uses direct addressing. The operand 63 is the actual address that the contents of ACC are stored to.
LDX 60 uses indexed addressing. The address actually accessed is 60 + the current contents of IX, not address 60 itself.

[3 marks]: 1 for each addressing mode correctly identified.

Part (b): Purpose of the value at address 62

The value 0 stored at address 62 is a sentinel value: it does not represent a real value to be summed, but marks the end of the list of values (at addresses 60, 61,…) that the program should add together, so the loop knows when to stop.

[1 mark]

Part (c): The Status Register

The register updated when CMP #0 executes is the Status Register (SR). Besides a compare instruction, its flags can also be set as a result of an arithmetic or logic operation (for example, an overflow or underflow), or by an interrupt flag being set.

[2 marks]: 1 for naming the Status Register (SR), 1 for a valid other event that sets its flags.

Part (d): Tracing the program

The loop repeats until LDX 60 loads the sentinel value (0) from address 62, at which point the comparison at CMP #0 is True and JPE 50 exits the loop.

Instruction executed	ACC	IX	Address 63
`LDM #0`	0	-	-
`STO 63`	0	-	0
`LDR #0`	0	0	0
`LDX 60`	4	0	0
`CMP #0`	4	0	0
`JPE 50` (not taken)	4	0	0
`ADD 63`	4	0	0
`STO 63`	4	0	4
`INC IX`	4	1	4
`JMP 43`	4	1	4
`LDX 60`	6	1	4
`CMP #0`	6	1	4
`JPE 50` (not taken)	6	1	4
`ADD 63`	10	1	4
`STO 63`	10	1	10
`INC IX`	10	2	10
`JMP 43`	10	2	10
`LDX 60`	0	2	10
`CMP #0`	0	2	10
`JPE 50` (taken)	0	2	10
`LDD 63`	10	2	10
`END`	10	2	10

The loop runs for the two real data values (4, then 6), adding each to the running total held at address 63. On the third pass, LDX 60 loads the sentinel (0) from address 62 (60 + IX, with IX = 2), the compare is now True, and JPE 50 jumps out of the loop before this sentinel is added. LDD 63 then copies the completed total back into ACC before END stops the program.

[5 marks]: marks awarded for correctly tracing IX incrementing once per pass (0, then 1, then 2), correctly updating address 63 to 4 then 10, correctly identifying the loop exits on the third pass (when the sentinel is loaded), and the correct final value ACC = 10.

Final answers

(a) LDM #0 = immediate; STO 63 = direct; LDX 60 = indexed.
(b) A sentinel marking the end of the list of values to sum.
(c) Status Register (SR); also set by, for example, an arithmetic overflow/underflow or an interrupt flag.
(d) Final ACC = 10, IX = 2, address 63 = 10 (matching 4 + 6 = 10).

Common mistakes

In (a), identifying LDX 60 as direct addressing rather than indexed addressing, by overlooking that the address actually accessed is 60 plus the current contents of IX, not address 60 itself.
In (b), describing address 62 as holding 'the third value to be summed', rather than recognising that 0 is a sentinel marking the end of the list, and is not itself added to the total.
In (c), naming the Accumulator or the Index Register as the register updated by CMP, rather than the Status Register (SR).
In (d), reusing IX from the previous loop pass instead of using its current, already-incremented value when working out the address accessed by LDX 60, so the wrong array element is read.
In (d), treating the value freshly loaded into ACC by LDX 60 as already being the running total, rather than recognising that ADD 63 must run afterwards to add it to the total stored at address 63.